The graph above shows the performance of Hydra flash memory when compared to other storage devices. Click on the image to have a bigger view.
Researchers Yoon Jae Seong and coauthors from Seoul National University have developed Hydra which takes the advantage of parallelism from multiple flash memory chips. They used various design methods to implement this technique. In the upcoming issue of IEEE transactions on computers, the research study will be published.
They have come up with the Hydra architecture which will efficiently be using the concept of  parallelism inherent in multiple flash memory chips. Hydra will help a lot to improve some of the troublesome shortcomings of NAND flash chips, which were designed primarily for bulk storage applications.
Using the new architecture, Hydra can operate on multiple chips simultaneously, which helps to increase the speed & also four 40MB/s buses when combined together can achieve a collective bandwidth of 160 MB/s. It also eliminates idle time that occur during data transfer.